1. Field of the Invention
The present invention relates to fast page readout used in a semiconductor memory device and, more particularly, to the semiconductor memory device performing division readout.
2. Description of the Related Art
In a conventional semiconductor memory device such as a flash memory, page readout has been used to read out and latch data of a few words in a lump by sense amplifiers and to fast output the data having a desired address only by the control at an output side. Specifically, during a first access, namely, an initial access, for example, plural data is latched in a lump. Then, the latched data is fast outputted by switching at the output side. In the conventional semiconductor memory device, the data of a few words, for example, data of 8 words (16 I/Os per word) has been simultaneously read out by the sense amplifiers of 8xc3x9716=128 in number.
The page readout does not increase current consumed by cell decode even the number of data increases. Specifically, although additional current is required to open a plurality of bit lines, there is no increase in current by the amounts of word line and predecode, so that the entire consumption current is not greatly affected. Compared to this, current consumed by the sense amplifier increases in proportion to the number of data. This is because each bit line is connected to each sense amplifier. As a result, when loads of all the sense amplifiers charge the data lines at a time, the consumption current momentarily increases to cause voltage drop and power noise. FIG. 8 shows a diagrammatic block diagram of the conventional semiconductor memory device. A plurality of memory cells 30 are respectively grouped by a unit of the plural number thereof. A plurality of data lines 31 are connected to each of the memory cells 30. These data lines 31 are grouped and connected to a plurality of grouped sense amplifiers 32. The number of the sense amplifiers 32 prepared in each group is, for example, 16. The 16 sense amplifiers in number correspond to 16 I/Os in number per word. In the structure shown in FIG. 8, 8 groups of the sense amplifiers 32, namely, 128 in number being a product of 16 and 8, are provided. The sense amplifiers 32 are provided inside a peripheral circuit area of the semiconductor memory device that differs from its memory cell area. Here, the sense amplifiers to be divided can be set by a proper unit such as 1 word, 2 words, and the like. Here, it is set to be every 8 words.
A sense amplifier enable signal with the same timing is inputted in each sense amplifier 32. This sense amplifier enable signal is outputted from a single sense amplifier enable signal generation circuit 33.
Next, operation of the conventional semiconductor memory device shown in FIG. 8 will be explained referring to FIG. 9 that shows timing of signals inputted and outputted to each structure in FIG. 8. An address signal is inputted to designate a memory cell to be accessed, and thereafter the sense amplifier enable signals to be inputted into each sense amplifier 32 arise simultaneously from LOW level to HIGH level so that all the sense amplifiers 32 are activated. Concurrently with the activation of the sense amplifiers 32, initial current is consumed in each sense amplifier 32. When the sense amplifiers 32 are activated, memory cells 30 that are connected to the sense amplifiers 32 are accessed. In this manner, the sense amplifiers are activated and data read out from the memory cells is outputted from I/Os (not shown).
The consumption current shown at the very bottom section in FIG. 9 momentarily and drastically increases just after all the sense amplifiers are activated, then becomes a constant state, and recovers to an initial value after the readout completes. Specifically, since maximum instantaneous consumption current is the sum of the initial consumption current in each activated sense amplifier and the time for each sense amplifier to start its activation is identical, the instantaneous consumption current extremely increases.
In addition, data amount (the number of words) to be read out tends to increase in the future due to further fast access. In this page readout, read operation is performed by the number of sense amplifiers that correspond to the data amount (the number of words) to be simultaneously read out, so that the more the data amount increases, the more the consumption current in that instant increases.
The following problems arise in the above-described conventional semiconductor memory device.
When power supply ability at a system side using the semiconductor memory device is poor, power voltage drop occurs in this instant and power noise occurs due to drastic current consumption, which may cause to lower readout ability of the semiconductor memory device and may cause its malfunction as well as malfunction in other devices mounted on the system. In a flash memory, when power drop of the system occurs, writing and erasing operation may run down. Particularly in a mobile electronic device and the like, the use of a battery tends to lower power supply ability for a semiconductor memory device built in the mobile electronic device, so that an increase in the instantaneous consumption current has a great impact thereon. In addition, concurrently with a technology trend of fast data readout, when data length increases, for example, from 16 to 32 in number, the consumption current increases.
In the conventional art, in a case of 8 words, the instantaneous consumption current flows, for example, by a several 100 mA. When its wiring resistance is assumed to be 1 ohm, voltage drop around the circuit becomes xe2x88x920, several V and characteristic deterioration occurs.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device, comprises;
a plurality of sense amplifiers divided into a plurality of groups, each of the groups being a unit of a page readout operation;
a sense amplifier control signal generation circuit which outputs a sense amplifier control signal for enabling the sense amplifiers of each group and disabling the sense amplifiers of each group, wherein the sense amplifier control signal enables and disables the sense amplifiers of a part of the groups at different timing from the sense amplifiers of other groups; and
a plurality of memory cells connected to the sense amplifiers via data lines.